Magnetoelectronic devices, spin electronic devices and spintronic devices are synonymous terms for devices that use the effects predominantly caused by electron spin. Magnetoelectronics effects are used in numerous information devices, and provide non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. Magnetoresistive random access memory (MRAM) devices are well-known magnetoelectronics information devices.
The architecture for MRAM devices is composed of an array of memory cells. Each memory cell comprises a memory element (e.g., a giant magnetoresistance (GMR) element or a magnetic tunnel junction (MTJ) element) in electrical communication with a transistor through an interconnect stack. The memory elements are programmed by the magnetic field created from current-carrying conductors. Typically, two current-carrying conductors, the “digit line” and the “bit line”, are arranged in cross point matrix to provide magnetic fields for programming of the memory element. Because the digit line usually is formed underlying the memory element so that the memory element may be magnetically coupled to the digit line, the interconnect stack that couples the memory element to the transistor typically is formed, using standard CMOS processing, offset from the memory element.
The interconnect stack is formed utilizing a number of via and metallization layers. The via that electrically couples the interconnect stack to the memory element often is referred to as the MVia. Present day methods for forming MVias in an MRAM device often produce undesirable results and challenges. For example, often the MVia is connected to the interconnect stack to the transistor by a digit line landing pad, which typically is formed at the same time the digit line is formed. However, the simultaneous formation of the digit line landing pad and the digit line often results in the deposition in the digit line landing pad of cladding material that is used to create the digit line. Cladding material in the digit line landing pad may cause the digit line landing pad to exert undesirable magnetic effects on the memory element.
In addition, in processes in which the digit line is formed before the MVia, the digit line typically is capped with a capping layer that serves to protect the metal of the digit line, usually copper, from diffusing out of the digit line and from subsequent processing steps. Formation of the MVia then may involve the blanket deposition of a barrier layer and copper into a via void space formed in a dielectric material layer in which the digit line is formed. The barrier layer minimizes the diffusion of the copper into the dielectric material layer. After deposition of the barrier layer and the copper into the via void space, any excess barrier layer and copper deposited outside the via void space and overlying the capping layer is removed, typically by a process such as chemical-mechanical polishing, electrochemical-mechanical polishing, or the like. However, such removal processes often result in roughness and non-uniform thickness of the remaining capping layer. Because the distance between the digit line and a memory element subsequently formed overlying the capping layer often is designed to be relatively thin, in the range of about 5 to 1000 angstroms, and uniform, both phenomena may have adverse affects on the formation and/or operation of the subsequently formed memory element.
Further, when copper is deposited into the via void space to form the MVia, a copper capping layer typically is deposited overlying the copper via, and consequently the digit line, to minimize copper diffusion from the via. However, such a capping layer may increases the distance between the digit line and the overlying memory element. In this regard, a relatively larger amount of current may be required to flow through the digit line to program the memory element.
Accordingly, it is desirable to provide a magnetoelectronic memory element structure and a method for fabricating the structure that results in a uniform thickness of material between the digit lines and the overlying memory elements. In addition, it is desirable to provide a magnetoelectronic memory element structure and a method for fabricating the structure that results in a smooth surface upon which a memory element may be deposited. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.